Threshold voltage is an important parameter to gauge characteristic of a MOSFET. In general, it can be used to determine when the MOSFET to be turned on when a bias is applied. For some non-volatile memory devices, such as EEPROM or Flash, the threshold voltage is used to determine the state of a memory cell in order to decide the cell is in “written” or “erase” status. With current trend of transistor density climbing, to minimize the deviation of cell's threshold voltage within a chip is more preferred to ensure a consistent and uniform performance.
The threshold voltage distribution is more crucial to a MLC (multi level cell) memory cell or cell array. FIG. 1 illustrates the distribution of threshold voltage of a 4-bit Flash MLC array. The MLC memory cell store four different voltages by charging the floating gate of a transistor to four different voltage levels such as, “1”, “2”, “3”, and “4”. Therefore, a 4-bit Flash MLC cell can store four different written states according to the charge stored in the floating gate. Unfortunately, with the conventional arrangement, the threshold voltage of the first state Vt1, or called initial state threshold voltage usually has a wider distribution MLC array (11-14 respectively represents the initial voltage state for different cell in the array) and a part of initial states may overlap with the second state. The window loss between the initial and its neighboring state can make some memory cells undistinguishable or give an error read out signal. Thus, an improvement to narrow the threshold voltage distribution for a MOSFET semiconductor structure, especially for the initial state threshold voltage is needed.